Integrated circuit memory devices such as read only memories (ROMs), random access memories (RAMs) and various other types of integrated circuit memories are widely used in electronics systems. As shown in FIG. 1, an integrated circuit memory device includes a plurality of unit cell arrays UCA arranged in rows and columns, division word line driver blocks SWD located between columns of unit cell arrays, and sense amplifier blocks SAB located between unit cell arrays in a column. The row decoder RD selects and drives one word line WL responsive to a row address which is provided from the row address line RAL. All memory cells within the row associated with the selected word line WL change an electrical charge on an associated bit line BL upon selection. The change in electrical charge on each bit line depends on whether a one or a zero is stored in the associated memory cell. This change in electrical charge is amplified by a corresponding sense amplifier.
A column selection line CSL is selectively driven by a column decoder CD in response to a column address provided by the column address line CAL. Accordingly, when both the word line WL and the column selection line CSL for a predetermined memory cell are selected, data from that memory cell is amplified by the associated sense amplifier and transmitted to the associated data line DL.
As also shown in FIG. 1, one column selection line CSL drives eight unit cell arrays UCA in a column. Two bits of data can be transmitted from sense amplifiers to corresponding data lines responsive to the selection of one column selection line. When a column access operation is performed, 16 bits of data can be transmitted. Accordingly, if the memory device is designed to output four bits of data, the 16 bits generated can be multiplexed through four, 4.times.1 multiplexers MUX and coupled to the four input/output pads DP.
Dynamic random access memories may require a latency period after data is output by a data access operation of a row chain before a row access operation is performed due to row precharge in one bank. In order to reduce the latency period and thereby increase the speed of the memory, a dynamic random access memory can have a structure including a plurality of banks which reduce the latency period by outputting data from another bank. The effect of the latency period can be reduced as the number of banks is increased because the possibility that the same bank is consecutively accessed is reduced. Accordingly, the data access capacity of a dynamic random access memory can be increased by dividing the memory into a larger number of banks.
An integrated circuit memory device including banks of unit cell arrays is illustrated in FIG. 2. As shown, each bank includes independent address transmission units, row and column decoders, sense amplifiers, data transmission units, and memory cells. Accordingly, this division into banks causes an increase in the chip size of the memory device.
The memory cell array is divided into four banks B0-B3. Each bank has a row decoder RDL such as a latch storage row decoder, and a column decoder CD. If the latch storage row decoder RDL selects and drives the word line of the corresponding bank in response to a row address and a bank selection signal provided by the row address line RAL and the bank information line BIL, data from the memory cell connected to the word line is amplified through the bit line and sense amplifier. Address information is stored in the row decoder so that a current driving state can be maintained in the first selected bank by the word line already selected even though the row address operation is performed in the next selected bank while the word line of the first selected bank is driven. After the data from the memory cell is amplified by the sense amplifier, it is transmitted to the data line DL if the column address and the bank selection signals are applied to the column decoder through the column address line CAL and the bank information line BIL and the two selected column selection lines CSL are driven in a selected bank. Because two column selection lines CSL are driven in one selected bank, four bits of data can be output from one selected bank.
The memory device of FIG. 2, however, may require a greater number of latch storage row decoders RDL and division word line driver blocks SWD than the memory device of FIG. 1. Furthermore, the memory device of FIG. 2 may require that the row address line RAL and the bank information line BIL be extended between the banks of unit cell arrays. In addition, this memory device may require additional wiring in the form of a data bus DB wherein the data bus is used to connect the data lines from each bank to the respective input/output pad DP. Accordingly, the memory device of FIG. 2 may require a larger chip area per unit of memory when compared to the memory device of FIG. 1.
In addition, the distances between the data lines and the associated input/output pads DP are different for data lines within the same bank. For example, assuming that the distance between the i-th data line and the corresponding data pad DP is established as D0i in the bank B0, the distance between the j-th data line and the corresponding input/output pad DP is D0j, the distance between the k-th data line and the input/output pad DP is D0k, and the distance between the l-th data line and the input/output pad DP is D01, the relationship therebetween is given as D0i.noteq.D0j.noteq.D0k.noteq.D01. As a result, line skew may result as data is transmitted across data lines of different lengths. Because the data transmission time is dependent on the length of the data line, the line skew may reduce or limit the speed at which data can be accessed.